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SPECIFICATION AND VERIFICATION OF SYSTOLIC ARRAYS

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Description:This book presents a formal method for specifying and verifying the correctness of systolic array designs. Such architectures are commonly found in the form of accelerators for digital signal, image, and video processing. These arrays can be quite complicated in topology and data flow. In the book, a formalism called STA is defined for these kinds of dynamic environments, with a survey of related techniques. A framework for specification and verification is established. Formal verification techniques to check the correctness of the systolic networks with respect to the algorithmic level specifications are explained. The book also presents a Prolog-based formal design verifier (named VSTA), developed to automate the verification process, as using a general purpose theorem prover is usually extremely time-consuming. Several application examples are included in the book to illustrate how formal techniques and the verifier can be used to automate proofs.We have made it easy for you to find a PDF Ebooks without any digging. And by having access to our ebooks online or by storing it on your computer, you have convenient answers with SPECIFICATION AND VERIFICATION OF SYSTOLIC ARRAYS. To get started finding SPECIFICATION AND VERIFICATION OF SYSTOLIC ARRAYS, you are right to find our website which has a comprehensive collection of manuals listed.
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ISBN: 9810238673

Description: This book presents a formal method for specifying and verifying the correctness of systolic array designs. Such architectures are commonly found in the form of accelerators for digital signal, image, and video processing. These arrays can be quite complicated in topology and data flow. In the book, a formalism called STA is defined for these kinds of dynamic environments, with a survey of related techniques. A framework for specification and verification is established. Formal verification techniques to check the correctness of the systolic networks with respect to the algorithmic level specifications are explained. The book also presents a Prolog-based formal design verifier (named VSTA), developed to automate the verification process, as using a general purpose theorem prover is usually extremely time-consuming. Several application examples are included in the book to illustrate how formal techniques and the verifier can be used to automate proofs.We have made it easy for you to find a PDF Ebooks without any digging. And by having access to our ebooks online or by storing it on your computer, you have convenient answers with SPECIFICATION AND VERIFICATION OF SYSTOLIC ARRAYS. To get started finding SPECIFICATION AND VERIFICATION OF SYSTOLIC ARRAYS, you are right to find our website which has a comprehensive collection of manuals listed.
Our library is the biggest of these that have literally hundreds of thousands of different products represented.

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SPECIFICATION AND VERIFICATION OF SYSTOLIC ARRAYS

SPECIFICATION AND VERIFICATION OF SYSTOLIC ARRAYS

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